Document Type

Technical Report

Publication Date


Technical Report Number



Algorithms for the parallel multiplication of two n bit binary numbers by an iterative array of logic cells are discussed. The regular interconnection structures of the multiplier array cell elements, which are ideal for VLSI implementation, are described. The speed and hardware complexity of two new iterative array algorithms, both of which require n cell delays for one n by n bit multiplication, are compared with a straight-forward iterative array algorithm having a 2n cell delay and its higher radix version having an n cell delay.