Date of Award

6-3-2004

Document Type

Thesis (Undergraduate)

Department or Program

Department of Computer Science

First Advisor

Prasad Jayanti

Abstract

This thesis proposes algorithms for implementing a atomic multi-word buffer, which can be accessed concurrently by multiple readers and a single writer, from the hardware-supported shared memory. The algorithms are required to be wait-free: each process reads or writes the multi-word buffer in a bounded number of its own steps, regardless of whether other processes are fast, slow or have crashed. Our first algorithm is built from multi-writer, multi-reader variables whereas the second algorithm is built from single-writer, multi-reader variables. For either algorithm, the worst-case running time of a read or a write operation on the m-word buffer is O(m). The space complexity of the algorithms is O(mn). Neither algorithm requires hardware support for any special synchronization instructions; the ability to read or write into any machine word is sufficient. The algorithms significantly improve on Peterson's algorithm, which has O(mn) time complexity for the write operation on the buffer.

Comments

Originally posted in the Dartmouth College Computer Science Technical Report Series, number TR2004-498.

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